;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.2
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar.inc
    INCLUDE cydeviceiar_trm.inc

/* OE */
OE_Sync_ctrl_reg__0__MASK EQU 0x01
OE_Sync_ctrl_reg__0__POS EQU 0
OE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
OE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
OE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
OE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
OE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
OE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
OE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
OE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
OE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
OE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
OE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL
OE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
OE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL
OE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
OE_Sync_ctrl_reg__MASK EQU 0x01
OE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
OE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
OE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK

/* SS */
SS__0__INTTYPE EQU CYREG_PICU3_INTTYPE3
SS__0__MASK EQU 0x08
SS__0__PC EQU CYREG_PRT3_PC3
SS__0__PORT EQU 3
SS__0__SHIFT EQU 3
SS__AG EQU CYREG_PRT3_AG
SS__AMUX EQU CYREG_PRT3_AMUX
SS__BIE EQU CYREG_PRT3_BIE
SS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
SS__BYP EQU CYREG_PRT3_BYP
SS__CTL EQU CYREG_PRT3_CTL
SS__DM0 EQU CYREG_PRT3_DM0
SS__DM1 EQU CYREG_PRT3_DM1
SS__DM2 EQU CYREG_PRT3_DM2
SS__DR EQU CYREG_PRT3_DR
SS__INP_DIS EQU CYREG_PRT3_INP_DIS
SS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SS__LCD_EN EQU CYREG_PRT3_LCD_EN
SS__MASK EQU 0x08
SS__PORT EQU 3
SS__PRT EQU CYREG_PRT3_PRT
SS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
SS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
SS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
SS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
SS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
SS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
SS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
SS__PS EQU CYREG_PRT3_PS
SS__SHIFT EQU 3
SS__SLW EQU CYREG_PRT3_SLW

/* ADC */
ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
ADC_bSAR_SEQ_ChannelCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
ADC_bSAR_SEQ_ChannelCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
ADC_bSAR_SEQ_ChannelCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
ADC_bSAR_SEQ_ChannelCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
ADC_bSAR_SEQ_ChannelCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
ADC_bSAR_SEQ_ChannelCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
ADC_bSAR_SEQ_ChannelCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
ADC_bSAR_SEQ_ChannelCounter__CONTROL_REG EQU CYREG_B0_UDB03_CTL
ADC_bSAR_SEQ_ChannelCounter__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
ADC_bSAR_SEQ_ChannelCounter__COUNT_REG EQU CYREG_B0_UDB03_CTL
ADC_bSAR_SEQ_ChannelCounter__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
ADC_bSAR_SEQ_ChannelCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
ADC_bSAR_SEQ_ChannelCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
ADC_bSAR_SEQ_ChannelCounter__PERIOD_REG EQU CYREG_B0_UDB03_MSK
ADC_bSAR_SEQ_ChannelCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
ADC_bSAR_SEQ_ChannelCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
ADC_bSAR_SEQ_ChannelCounter_ST__MASK_REG EQU CYREG_B0_UDB03_MSK
ADC_bSAR_SEQ_ChannelCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
ADC_bSAR_SEQ_ChannelCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_REG EQU CYREG_B0_UDB03_ST
ADC_bSAR_SEQ_CtrlReg__0__MASK EQU 0x01
ADC_bSAR_SEQ_CtrlReg__0__POS EQU 0
ADC_bSAR_SEQ_CtrlReg__1__MASK EQU 0x02
ADC_bSAR_SEQ_CtrlReg__1__POS EQU 1
ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
ADC_bSAR_SEQ_CtrlReg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
ADC_bSAR_SEQ_CtrlReg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
ADC_bSAR_SEQ_CtrlReg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
ADC_bSAR_SEQ_CtrlReg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
ADC_bSAR_SEQ_CtrlReg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
ADC_bSAR_SEQ_CtrlReg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
ADC_bSAR_SEQ_CtrlReg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
ADC_bSAR_SEQ_CtrlReg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
ADC_bSAR_SEQ_CtrlReg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
ADC_bSAR_SEQ_CtrlReg__COUNT_REG EQU CYREG_B0_UDB02_CTL
ADC_bSAR_SEQ_CtrlReg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
ADC_bSAR_SEQ_CtrlReg__MASK EQU 0x03
ADC_bSAR_SEQ_CtrlReg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
ADC_bSAR_SEQ_CtrlReg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
ADC_bSAR_SEQ_CtrlReg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
ADC_bSAR_SEQ_EOCSts__0__MASK EQU 0x01
ADC_bSAR_SEQ_EOCSts__0__POS EQU 0
ADC_bSAR_SEQ_EOCSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
ADC_bSAR_SEQ_EOCSts__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
ADC_bSAR_SEQ_EOCSts__MASK EQU 0x01
ADC_bSAR_SEQ_EOCSts__MASK_REG EQU CYREG_B0_UDB05_MSK
ADC_bSAR_SEQ_EOCSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
ADC_bSAR_SEQ_EOCSts__STATUS_REG EQU CYREG_B0_UDB05_ST
ADC_FinalBuf__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
ADC_FinalBuf__DRQ_NUMBER EQU 0
ADC_FinalBuf__NUMBEROF_TDS EQU 0
ADC_FinalBuf__PRIORITY EQU 2
ADC_FinalBuf__TERMIN_EN EQU 0
ADC_FinalBuf__TERMIN_SEL EQU 0
ADC_FinalBuf__TERMOUT0_EN EQU 1
ADC_FinalBuf__TERMOUT0_SEL EQU 0
ADC_FinalBuf__TERMOUT1_EN EQU 0
ADC_FinalBuf__TERMOUT1_SEL EQU 0
ADC_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
ADC_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
ADC_IntClock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
ADC_IntClock__CFG2_SRC_SEL_MASK EQU 0x07
ADC_IntClock__INDEX EQU 0x00
ADC_IntClock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ADC_IntClock__PM_ACT_MSK EQU 0x01
ADC_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ADC_IntClock__PM_STBY_MSK EQU 0x01
ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ADC_IRQ__INTC_MASK EQU 0x01
ADC_IRQ__INTC_NUMBER EQU 0
ADC_IRQ__INTC_PRIOR_NUM EQU 7
ADC_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
ADC_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ADC_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
ADC_SAR_ADC_SAR__CLK EQU CYREG_SAR0_CLK
ADC_SAR_ADC_SAR__CSR0 EQU CYREG_SAR0_CSR0
ADC_SAR_ADC_SAR__CSR1 EQU CYREG_SAR0_CSR1
ADC_SAR_ADC_SAR__CSR2 EQU CYREG_SAR0_CSR2
ADC_SAR_ADC_SAR__CSR3 EQU CYREG_SAR0_CSR3
ADC_SAR_ADC_SAR__CSR4 EQU CYREG_SAR0_CSR4
ADC_SAR_ADC_SAR__CSR5 EQU CYREG_SAR0_CSR5
ADC_SAR_ADC_SAR__CSR6 EQU CYREG_SAR0_CSR6
ADC_SAR_ADC_SAR__PM_ACT_CFG EQU CYREG_PM_ACT_CFG11
ADC_SAR_ADC_SAR__PM_ACT_MSK EQU 0x01
ADC_SAR_ADC_SAR__PM_STBY_CFG EQU CYREG_PM_STBY_CFG11
ADC_SAR_ADC_SAR__PM_STBY_MSK EQU 0x01
ADC_SAR_ADC_SAR__SW0 EQU CYREG_SAR0_SW0
ADC_SAR_ADC_SAR__SW2 EQU CYREG_SAR0_SW2
ADC_SAR_ADC_SAR__SW3 EQU CYREG_SAR0_SW3
ADC_SAR_ADC_SAR__SW4 EQU CYREG_SAR0_SW4
ADC_SAR_ADC_SAR__SW6 EQU CYREG_SAR0_SW6
ADC_SAR_ADC_SAR__TR0 EQU CYREG_SAR0_TR0
ADC_SAR_ADC_SAR__WRK0 EQU CYREG_SAR0_WRK0
ADC_SAR_ADC_SAR__WRK1 EQU CYREG_SAR0_WRK1
ADC_TempBuf__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
ADC_TempBuf__DRQ_NUMBER EQU 1
ADC_TempBuf__NUMBEROF_TDS EQU 0
ADC_TempBuf__PRIORITY EQU 2
ADC_TempBuf__TERMIN_EN EQU 0
ADC_TempBuf__TERMIN_SEL EQU 0
ADC_TempBuf__TERMOUT0_EN EQU 1
ADC_TempBuf__TERMOUT0_SEL EQU 1
ADC_TempBuf__TERMOUT1_EN EQU 0
ADC_TempBuf__TERMOUT1_SEL EQU 0

/* MISO */
MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
MISO__0__MASK EQU 0x10
MISO__0__PC EQU CYREG_PRT3_PC4
MISO__0__PORT EQU 3
MISO__0__SHIFT EQU 4
MISO__AG EQU CYREG_PRT3_AG
MISO__AMUX EQU CYREG_PRT3_AMUX
MISO__BIE EQU CYREG_PRT3_BIE
MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
MISO__BYP EQU CYREG_PRT3_BYP
MISO__CTL EQU CYREG_PRT3_CTL
MISO__DM0 EQU CYREG_PRT3_DM0
MISO__DM1 EQU CYREG_PRT3_DM1
MISO__DM2 EQU CYREG_PRT3_DM2
MISO__DR EQU CYREG_PRT3_DR
MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
MISO__MASK EQU 0x10
MISO__PORT EQU 3
MISO__PRT EQU CYREG_PRT3_PRT
MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
MISO__PS EQU CYREG_PRT3_PS
MISO__SHIFT EQU 4
MISO__SLW EQU CYREG_PRT3_SLW

/* MOSI */
MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE0
MOSI__0__MASK EQU 0x01
MOSI__0__PC EQU CYREG_PRT3_PC0
MOSI__0__PORT EQU 3
MOSI__0__SHIFT EQU 0
MOSI__AG EQU CYREG_PRT3_AG
MOSI__AMUX EQU CYREG_PRT3_AMUX
MOSI__BIE EQU CYREG_PRT3_BIE
MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
MOSI__BYP EQU CYREG_PRT3_BYP
MOSI__CTL EQU CYREG_PRT3_CTL
MOSI__DM0 EQU CYREG_PRT3_DM0
MOSI__DM1 EQU CYREG_PRT3_DM1
MOSI__DM2 EQU CYREG_PRT3_DM2
MOSI__DR EQU CYREG_PRT3_DR
MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
MOSI__MASK EQU 0x01
MOSI__PORT EQU 3
MOSI__PRT EQU CYREG_PRT3_PRT
MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
MOSI__PS EQU CYREG_PRT3_PS
MOSI__SHIFT EQU 0
MOSI__SLW EQU CYREG_PRT3_SLW

/* SCLK */
SCLK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
SCLK__0__MASK EQU 0x02
SCLK__0__PC EQU CYREG_PRT3_PC1
SCLK__0__PORT EQU 3
SCLK__0__SHIFT EQU 1
SCLK__AG EQU CYREG_PRT3_AG
SCLK__AMUX EQU CYREG_PRT3_AMUX
SCLK__BIE EQU CYREG_PRT3_BIE
SCLK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
SCLK__BYP EQU CYREG_PRT3_BYP
SCLK__CTL EQU CYREG_PRT3_CTL
SCLK__DM0 EQU CYREG_PRT3_DM0
SCLK__DM1 EQU CYREG_PRT3_DM1
SCLK__DM2 EQU CYREG_PRT3_DM2
SCLK__DR EQU CYREG_PRT3_DR
SCLK__INP_DIS EQU CYREG_PRT3_INP_DIS
SCLK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SCLK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SCLK__LCD_EN EQU CYREG_PRT3_LCD_EN
SCLK__MASK EQU 0x02
SCLK__PORT EQU 3
SCLK__PRT EQU CYREG_PRT3_PRT
SCLK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
SCLK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
SCLK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
SCLK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
SCLK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
SCLK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
SCLK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
SCLK__PS EQU CYREG_PRT3_PS
SCLK__SHIFT EQU 1
SCLK__SLW EQU CYREG_PRT3_SLW

/* SPIS */
SPIS_BSPIS_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SPIS_BSPIS_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SPIS_BSPIS_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SPIS_BSPIS_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SPIS_BSPIS_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SPIS_BSPIS_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SPIS_BSPIS_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SPIS_BSPIS_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SPIS_BSPIS_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SPIS_BSPIS_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SPIS_BSPIS_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SPIS_BSPIS_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SPIS_BSPIS_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
SPIS_BSPIS_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SPIS_BSPIS_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SPIS_BSPIS_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SPIS_BSPIS_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
SPIS_BSPIS_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SPIS_BSPIS_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SPIS_BSPIS_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
SPIS_BSPIS_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SPIS_BSPIS_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SPIS_BSPIS_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SPIS_BSPIS_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SPIS_BSPIS_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SPIS_BSPIS_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
SPIS_BSPIS_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SPIS_BSPIS_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SPIS_BSPIS_RxStsReg__3__MASK EQU 0x08
SPIS_BSPIS_RxStsReg__3__POS EQU 3
SPIS_BSPIS_RxStsReg__4__MASK EQU 0x10
SPIS_BSPIS_RxStsReg__4__POS EQU 4
SPIS_BSPIS_RxStsReg__5__MASK EQU 0x20
SPIS_BSPIS_RxStsReg__5__POS EQU 5
SPIS_BSPIS_RxStsReg__6__MASK EQU 0x40
SPIS_BSPIS_RxStsReg__6__POS EQU 6
SPIS_BSPIS_RxStsReg__MASK EQU 0x78
SPIS_BSPIS_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SPIS_BSPIS_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SPIS_BSPIS_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SPIS_BSPIS_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
SPIS_BSPIS_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
SPIS_BSPIS_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
SPIS_BSPIS_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
SPIS_BSPIS_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SPIS_BSPIS_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
SPIS_BSPIS_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
SPIS_BSPIS_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
SPIS_BSPIS_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
SPIS_BSPIS_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
SPIS_BSPIS_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
SPIS_BSPIS_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
SPIS_BSPIS_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
SPIS_BSPIS_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SPIS_BSPIS_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
SPIS_BSPIS_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
SPIS_BSPIS_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
SPIS_BSPIS_TxStsReg__0__MASK EQU 0x01
SPIS_BSPIS_TxStsReg__0__POS EQU 0
SPIS_BSPIS_TxStsReg__1__MASK EQU 0x02
SPIS_BSPIS_TxStsReg__1__POS EQU 1
SPIS_BSPIS_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SPIS_BSPIS_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SPIS_BSPIS_TxStsReg__2__MASK EQU 0x04
SPIS_BSPIS_TxStsReg__2__POS EQU 2
SPIS_BSPIS_TxStsReg__6__MASK EQU 0x40
SPIS_BSPIS_TxStsReg__6__POS EQU 6
SPIS_BSPIS_TxStsReg__MASK EQU 0x47
SPIS_BSPIS_TxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
SPIS_BSPIS_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SPIS_BSPIS_TxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
SPIS_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SPIS_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SPIS_IntClock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SPIS_IntClock__CFG2_SRC_SEL_MASK EQU 0x07
SPIS_IntClock__INDEX EQU 0x01
SPIS_IntClock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SPIS_IntClock__PM_ACT_MSK EQU 0x02
SPIS_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SPIS_IntClock__PM_STBY_MSK EQU 0x02
SPIS_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SPIS_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SPIS_RxInternalInterrupt__INTC_MASK EQU 0x02
SPIS_RxInternalInterrupt__INTC_NUMBER EQU 1
SPIS_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7
SPIS_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
SPIS_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SPIS_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SPIS_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SPIS_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SPIS_TxInternalInterrupt__INTC_MASK EQU 0x04
SPIS_TxInternalInterrupt__INTC_NUMBER EQU 2
SPIS_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7
SPIS_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
SPIS_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SPIS_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

/* Therm1 */
Therm1__0__INTTYPE EQU CYREG_PICU4_INTTYPE0
Therm1__0__MASK EQU 0x01
Therm1__0__PC EQU CYREG_PRT4_PC0
Therm1__0__PORT EQU 4
Therm1__0__SHIFT EQU 0
Therm1__AG EQU CYREG_PRT4_AG
Therm1__AMUX EQU CYREG_PRT4_AMUX
Therm1__BIE EQU CYREG_PRT4_BIE
Therm1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm1__BYP EQU CYREG_PRT4_BYP
Therm1__CTL EQU CYREG_PRT4_CTL
Therm1__DM0 EQU CYREG_PRT4_DM0
Therm1__DM1 EQU CYREG_PRT4_DM1
Therm1__DM2 EQU CYREG_PRT4_DM2
Therm1__DR EQU CYREG_PRT4_DR
Therm1__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm1__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm1__MASK EQU 0x01
Therm1__PORT EQU 4
Therm1__PRT EQU CYREG_PRT4_PRT
Therm1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm1__PS EQU CYREG_PRT4_PS
Therm1__SHIFT EQU 0
Therm1__SLW EQU CYREG_PRT4_SLW

/* Therm2 */
Therm2__0__INTTYPE EQU CYREG_PICU4_INTTYPE1
Therm2__0__MASK EQU 0x02
Therm2__0__PC EQU CYREG_PRT4_PC1
Therm2__0__PORT EQU 4
Therm2__0__SHIFT EQU 1
Therm2__AG EQU CYREG_PRT4_AG
Therm2__AMUX EQU CYREG_PRT4_AMUX
Therm2__BIE EQU CYREG_PRT4_BIE
Therm2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm2__BYP EQU CYREG_PRT4_BYP
Therm2__CTL EQU CYREG_PRT4_CTL
Therm2__DM0 EQU CYREG_PRT4_DM0
Therm2__DM1 EQU CYREG_PRT4_DM1
Therm2__DM2 EQU CYREG_PRT4_DM2
Therm2__DR EQU CYREG_PRT4_DR
Therm2__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm2__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm2__MASK EQU 0x02
Therm2__PORT EQU 4
Therm2__PRT EQU CYREG_PRT4_PRT
Therm2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm2__PS EQU CYREG_PRT4_PS
Therm2__SHIFT EQU 1
Therm2__SLW EQU CYREG_PRT4_SLW

/* Therm3 */
Therm3__0__INTTYPE EQU CYREG_PICU4_INTTYPE2
Therm3__0__MASK EQU 0x04
Therm3__0__PC EQU CYREG_PRT4_PC2
Therm3__0__PORT EQU 4
Therm3__0__SHIFT EQU 2
Therm3__AG EQU CYREG_PRT4_AG
Therm3__AMUX EQU CYREG_PRT4_AMUX
Therm3__BIE EQU CYREG_PRT4_BIE
Therm3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm3__BYP EQU CYREG_PRT4_BYP
Therm3__CTL EQU CYREG_PRT4_CTL
Therm3__DM0 EQU CYREG_PRT4_DM0
Therm3__DM1 EQU CYREG_PRT4_DM1
Therm3__DM2 EQU CYREG_PRT4_DM2
Therm3__DR EQU CYREG_PRT4_DR
Therm3__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm3__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm3__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm3__MASK EQU 0x04
Therm3__PORT EQU 4
Therm3__PRT EQU CYREG_PRT4_PRT
Therm3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm3__PS EQU CYREG_PRT4_PS
Therm3__SHIFT EQU 2
Therm3__SLW EQU CYREG_PRT4_SLW

/* Therm4 */
Therm4__0__INTTYPE EQU CYREG_PICU4_INTTYPE3
Therm4__0__MASK EQU 0x08
Therm4__0__PC EQU CYREG_PRT4_PC3
Therm4__0__PORT EQU 4
Therm4__0__SHIFT EQU 3
Therm4__AG EQU CYREG_PRT4_AG
Therm4__AMUX EQU CYREG_PRT4_AMUX
Therm4__BIE EQU CYREG_PRT4_BIE
Therm4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm4__BYP EQU CYREG_PRT4_BYP
Therm4__CTL EQU CYREG_PRT4_CTL
Therm4__DM0 EQU CYREG_PRT4_DM0
Therm4__DM1 EQU CYREG_PRT4_DM1
Therm4__DM2 EQU CYREG_PRT4_DM2
Therm4__DR EQU CYREG_PRT4_DR
Therm4__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm4__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm4__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm4__MASK EQU 0x08
Therm4__PORT EQU 4
Therm4__PRT EQU CYREG_PRT4_PRT
Therm4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm4__PS EQU CYREG_PRT4_PS
Therm4__SHIFT EQU 3
Therm4__SLW EQU CYREG_PRT4_SLW

/* Therm5 */
Therm5__0__INTTYPE EQU CYREG_PICU4_INTTYPE4
Therm5__0__MASK EQU 0x10
Therm5__0__PC EQU CYREG_PRT4_PC4
Therm5__0__PORT EQU 4
Therm5__0__SHIFT EQU 4
Therm5__AG EQU CYREG_PRT4_AG
Therm5__AMUX EQU CYREG_PRT4_AMUX
Therm5__BIE EQU CYREG_PRT4_BIE
Therm5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm5__BYP EQU CYREG_PRT4_BYP
Therm5__CTL EQU CYREG_PRT4_CTL
Therm5__DM0 EQU CYREG_PRT4_DM0
Therm5__DM1 EQU CYREG_PRT4_DM1
Therm5__DM2 EQU CYREG_PRT4_DM2
Therm5__DR EQU CYREG_PRT4_DR
Therm5__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm5__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm5__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm5__MASK EQU 0x10
Therm5__PORT EQU 4
Therm5__PRT EQU CYREG_PRT4_PRT
Therm5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm5__PS EQU CYREG_PRT4_PS
Therm5__SHIFT EQU 4
Therm5__SLW EQU CYREG_PRT4_SLW

/* Therm6 */
Therm6__0__INTTYPE EQU CYREG_PICU4_INTTYPE5
Therm6__0__MASK EQU 0x20
Therm6__0__PC EQU CYREG_PRT4_PC5
Therm6__0__PORT EQU 4
Therm6__0__SHIFT EQU 5
Therm6__AG EQU CYREG_PRT4_AG
Therm6__AMUX EQU CYREG_PRT4_AMUX
Therm6__BIE EQU CYREG_PRT4_BIE
Therm6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm6__BYP EQU CYREG_PRT4_BYP
Therm6__CTL EQU CYREG_PRT4_CTL
Therm6__DM0 EQU CYREG_PRT4_DM0
Therm6__DM1 EQU CYREG_PRT4_DM1
Therm6__DM2 EQU CYREG_PRT4_DM2
Therm6__DR EQU CYREG_PRT4_DR
Therm6__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm6__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm6__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm6__MASK EQU 0x20
Therm6__PORT EQU 4
Therm6__PRT EQU CYREG_PRT4_PRT
Therm6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm6__PS EQU CYREG_PRT4_PS
Therm6__SHIFT EQU 5
Therm6__SLW EQU CYREG_PRT4_SLW

/* Therm7 */
Therm7__0__INTTYPE EQU CYREG_PICU4_INTTYPE6
Therm7__0__MASK EQU 0x40
Therm7__0__PC EQU CYREG_PRT4_PC6
Therm7__0__PORT EQU 4
Therm7__0__SHIFT EQU 6
Therm7__AG EQU CYREG_PRT4_AG
Therm7__AMUX EQU CYREG_PRT4_AMUX
Therm7__BIE EQU CYREG_PRT4_BIE
Therm7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm7__BYP EQU CYREG_PRT4_BYP
Therm7__CTL EQU CYREG_PRT4_CTL
Therm7__DM0 EQU CYREG_PRT4_DM0
Therm7__DM1 EQU CYREG_PRT4_DM1
Therm7__DM2 EQU CYREG_PRT4_DM2
Therm7__DR EQU CYREG_PRT4_DR
Therm7__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm7__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm7__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm7__MASK EQU 0x40
Therm7__PORT EQU 4
Therm7__PRT EQU CYREG_PRT4_PRT
Therm7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm7__PS EQU CYREG_PRT4_PS
Therm7__SHIFT EQU 6
Therm7__SLW EQU CYREG_PRT4_SLW

/* Therm8 */
Therm8__0__INTTYPE EQU CYREG_PICU4_INTTYPE7
Therm8__0__MASK EQU 0x80
Therm8__0__PC EQU CYREG_PRT4_PC7
Therm8__0__PORT EQU 4
Therm8__0__SHIFT EQU 7
Therm8__AG EQU CYREG_PRT4_AG
Therm8__AMUX EQU CYREG_PRT4_AMUX
Therm8__BIE EQU CYREG_PRT4_BIE
Therm8__BIT_MASK EQU CYREG_PRT4_BIT_MASK
Therm8__BYP EQU CYREG_PRT4_BYP
Therm8__CTL EQU CYREG_PRT4_CTL
Therm8__DM0 EQU CYREG_PRT4_DM0
Therm8__DM1 EQU CYREG_PRT4_DM1
Therm8__DM2 EQU CYREG_PRT4_DM2
Therm8__DR EQU CYREG_PRT4_DR
Therm8__INP_DIS EQU CYREG_PRT4_INP_DIS
Therm8__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
Therm8__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
Therm8__LCD_EN EQU CYREG_PRT4_LCD_EN
Therm8__MASK EQU 0x80
Therm8__PORT EQU 4
Therm8__PRT EQU CYREG_PRT4_PRT
Therm8__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
Therm8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
Therm8__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
Therm8__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
Therm8__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
Therm8__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
Therm8__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
Therm8__PS EQU CYREG_PRT4_PS
Therm8__SHIFT EQU 7
Therm8__SLW EQU CYREG_PRT4_SLW

/* Therm9 */
Therm9__0__INTTYPE EQU CYREG_PICU6_INTTYPE0
Therm9__0__MASK EQU 0x01
Therm9__0__PC EQU CYREG_PRT6_PC0
Therm9__0__PORT EQU 6
Therm9__0__SHIFT EQU 0
Therm9__AG EQU CYREG_PRT6_AG
Therm9__AMUX EQU CYREG_PRT6_AMUX
Therm9__BIE EQU CYREG_PRT6_BIE
Therm9__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm9__BYP EQU CYREG_PRT6_BYP
Therm9__CTL EQU CYREG_PRT6_CTL
Therm9__DM0 EQU CYREG_PRT6_DM0
Therm9__DM1 EQU CYREG_PRT6_DM1
Therm9__DM2 EQU CYREG_PRT6_DM2
Therm9__DR EQU CYREG_PRT6_DR
Therm9__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm9__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm9__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm9__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm9__MASK EQU 0x01
Therm9__PORT EQU 6
Therm9__PRT EQU CYREG_PRT6_PRT
Therm9__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm9__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm9__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm9__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm9__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm9__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm9__PS EQU CYREG_PRT6_PS
Therm9__SHIFT EQU 0
Therm9__SLW EQU CYREG_PRT6_SLW

/* Therm10 */
Therm10__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
Therm10__0__MASK EQU 0x02
Therm10__0__PC EQU CYREG_PRT6_PC1
Therm10__0__PORT EQU 6
Therm10__0__SHIFT EQU 1
Therm10__AG EQU CYREG_PRT6_AG
Therm10__AMUX EQU CYREG_PRT6_AMUX
Therm10__BIE EQU CYREG_PRT6_BIE
Therm10__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm10__BYP EQU CYREG_PRT6_BYP
Therm10__CTL EQU CYREG_PRT6_CTL
Therm10__DM0 EQU CYREG_PRT6_DM0
Therm10__DM1 EQU CYREG_PRT6_DM1
Therm10__DM2 EQU CYREG_PRT6_DM2
Therm10__DR EQU CYREG_PRT6_DR
Therm10__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm10__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm10__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm10__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm10__MASK EQU 0x02
Therm10__PORT EQU 6
Therm10__PRT EQU CYREG_PRT6_PRT
Therm10__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm10__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm10__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm10__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm10__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm10__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm10__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm10__PS EQU CYREG_PRT6_PS
Therm10__SHIFT EQU 1
Therm10__SLW EQU CYREG_PRT6_SLW

/* Therm11 */
Therm11__0__INTTYPE EQU CYREG_PICU6_INTTYPE2
Therm11__0__MASK EQU 0x04
Therm11__0__PC EQU CYREG_PRT6_PC2
Therm11__0__PORT EQU 6
Therm11__0__SHIFT EQU 2
Therm11__AG EQU CYREG_PRT6_AG
Therm11__AMUX EQU CYREG_PRT6_AMUX
Therm11__BIE EQU CYREG_PRT6_BIE
Therm11__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm11__BYP EQU CYREG_PRT6_BYP
Therm11__CTL EQU CYREG_PRT6_CTL
Therm11__DM0 EQU CYREG_PRT6_DM0
Therm11__DM1 EQU CYREG_PRT6_DM1
Therm11__DM2 EQU CYREG_PRT6_DM2
Therm11__DR EQU CYREG_PRT6_DR
Therm11__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm11__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm11__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm11__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm11__MASK EQU 0x04
Therm11__PORT EQU 6
Therm11__PRT EQU CYREG_PRT6_PRT
Therm11__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm11__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm11__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm11__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm11__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm11__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm11__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm11__PS EQU CYREG_PRT6_PS
Therm11__SHIFT EQU 2
Therm11__SLW EQU CYREG_PRT6_SLW

/* Therm12 */
Therm12__0__INTTYPE EQU CYREG_PICU6_INTTYPE3
Therm12__0__MASK EQU 0x08
Therm12__0__PC EQU CYREG_PRT6_PC3
Therm12__0__PORT EQU 6
Therm12__0__SHIFT EQU 3
Therm12__AG EQU CYREG_PRT6_AG
Therm12__AMUX EQU CYREG_PRT6_AMUX
Therm12__BIE EQU CYREG_PRT6_BIE
Therm12__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm12__BYP EQU CYREG_PRT6_BYP
Therm12__CTL EQU CYREG_PRT6_CTL
Therm12__DM0 EQU CYREG_PRT6_DM0
Therm12__DM1 EQU CYREG_PRT6_DM1
Therm12__DM2 EQU CYREG_PRT6_DM2
Therm12__DR EQU CYREG_PRT6_DR
Therm12__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm12__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm12__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm12__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm12__MASK EQU 0x08
Therm12__PORT EQU 6
Therm12__PRT EQU CYREG_PRT6_PRT
Therm12__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm12__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm12__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm12__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm12__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm12__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm12__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm12__PS EQU CYREG_PRT6_PS
Therm12__SHIFT EQU 3
Therm12__SLW EQU CYREG_PRT6_SLW

/* Therm13 */
Therm13__0__INTTYPE EQU CYREG_PICU6_INTTYPE4
Therm13__0__MASK EQU 0x10
Therm13__0__PC EQU CYREG_PRT6_PC4
Therm13__0__PORT EQU 6
Therm13__0__SHIFT EQU 4
Therm13__AG EQU CYREG_PRT6_AG
Therm13__AMUX EQU CYREG_PRT6_AMUX
Therm13__BIE EQU CYREG_PRT6_BIE
Therm13__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm13__BYP EQU CYREG_PRT6_BYP
Therm13__CTL EQU CYREG_PRT6_CTL
Therm13__DM0 EQU CYREG_PRT6_DM0
Therm13__DM1 EQU CYREG_PRT6_DM1
Therm13__DM2 EQU CYREG_PRT6_DM2
Therm13__DR EQU CYREG_PRT6_DR
Therm13__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm13__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm13__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm13__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm13__MASK EQU 0x10
Therm13__PORT EQU 6
Therm13__PRT EQU CYREG_PRT6_PRT
Therm13__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm13__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm13__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm13__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm13__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm13__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm13__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm13__PS EQU CYREG_PRT6_PS
Therm13__SHIFT EQU 4
Therm13__SLW EQU CYREG_PRT6_SLW

/* Therm14 */
Therm14__0__INTTYPE EQU CYREG_PICU6_INTTYPE5
Therm14__0__MASK EQU 0x20
Therm14__0__PC EQU CYREG_PRT6_PC5
Therm14__0__PORT EQU 6
Therm14__0__SHIFT EQU 5
Therm14__AG EQU CYREG_PRT6_AG
Therm14__AMUX EQU CYREG_PRT6_AMUX
Therm14__BIE EQU CYREG_PRT6_BIE
Therm14__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Therm14__BYP EQU CYREG_PRT6_BYP
Therm14__CTL EQU CYREG_PRT6_CTL
Therm14__DM0 EQU CYREG_PRT6_DM0
Therm14__DM1 EQU CYREG_PRT6_DM1
Therm14__DM2 EQU CYREG_PRT6_DM2
Therm14__DR EQU CYREG_PRT6_DR
Therm14__INP_DIS EQU CYREG_PRT6_INP_DIS
Therm14__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
Therm14__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Therm14__LCD_EN EQU CYREG_PRT6_LCD_EN
Therm14__MASK EQU 0x20
Therm14__PORT EQU 6
Therm14__PRT EQU CYREG_PRT6_PRT
Therm14__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Therm14__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Therm14__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Therm14__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Therm14__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Therm14__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Therm14__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Therm14__PS EQU CYREG_PRT6_PS
Therm14__SHIFT EQU 5
Therm14__SLW EQU CYREG_PRT6_SLW

/* Address1 */
Address1__0__INTTYPE EQU CYREG_PICU2_INTTYPE0
Address1__0__MASK EQU 0x01
Address1__0__PC EQU CYREG_PRT2_PC0
Address1__0__PORT EQU 2
Address1__0__SHIFT EQU 0
Address1__AG EQU CYREG_PRT2_AG
Address1__AMUX EQU CYREG_PRT2_AMUX
Address1__BIE EQU CYREG_PRT2_BIE
Address1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Address1__BYP EQU CYREG_PRT2_BYP
Address1__CTL EQU CYREG_PRT2_CTL
Address1__DM0 EQU CYREG_PRT2_DM0
Address1__DM1 EQU CYREG_PRT2_DM1
Address1__DM2 EQU CYREG_PRT2_DM2
Address1__DR EQU CYREG_PRT2_DR
Address1__INP_DIS EQU CYREG_PRT2_INP_DIS
Address1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
Address1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Address1__LCD_EN EQU CYREG_PRT2_LCD_EN
Address1__MASK EQU 0x01
Address1__PORT EQU 2
Address1__PRT EQU CYREG_PRT2_PRT
Address1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Address1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Address1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Address1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Address1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Address1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Address1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Address1__PS EQU CYREG_PRT2_PS
Address1__SHIFT EQU 0
Address1__SLW EQU CYREG_PRT2_SLW

/* Address2 */
Address2__0__INTTYPE EQU CYREG_PICU2_INTTYPE1
Address2__0__MASK EQU 0x02
Address2__0__PC EQU CYREG_PRT2_PC1
Address2__0__PORT EQU 2
Address2__0__SHIFT EQU 1
Address2__AG EQU CYREG_PRT2_AG
Address2__AMUX EQU CYREG_PRT2_AMUX
Address2__BIE EQU CYREG_PRT2_BIE
Address2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Address2__BYP EQU CYREG_PRT2_BYP
Address2__CTL EQU CYREG_PRT2_CTL
Address2__DM0 EQU CYREG_PRT2_DM0
Address2__DM1 EQU CYREG_PRT2_DM1
Address2__DM2 EQU CYREG_PRT2_DM2
Address2__DR EQU CYREG_PRT2_DR
Address2__INP_DIS EQU CYREG_PRT2_INP_DIS
Address2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
Address2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Address2__LCD_EN EQU CYREG_PRT2_LCD_EN
Address2__MASK EQU 0x02
Address2__PORT EQU 2
Address2__PRT EQU CYREG_PRT2_PRT
Address2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Address2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Address2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Address2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Address2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Address2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Address2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Address2__PS EQU CYREG_PRT2_PS
Address2__SHIFT EQU 1
Address2__SLW EQU CYREG_PRT2_SLW

/* Address3 */
Address3__0__INTTYPE EQU CYREG_PICU2_INTTYPE2
Address3__0__MASK EQU 0x04
Address3__0__PC EQU CYREG_PRT2_PC2
Address3__0__PORT EQU 2
Address3__0__SHIFT EQU 2
Address3__AG EQU CYREG_PRT2_AG
Address3__AMUX EQU CYREG_PRT2_AMUX
Address3__BIE EQU CYREG_PRT2_BIE
Address3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Address3__BYP EQU CYREG_PRT2_BYP
Address3__CTL EQU CYREG_PRT2_CTL
Address3__DM0 EQU CYREG_PRT2_DM0
Address3__DM1 EQU CYREG_PRT2_DM1
Address3__DM2 EQU CYREG_PRT2_DM2
Address3__DR EQU CYREG_PRT2_DR
Address3__INP_DIS EQU CYREG_PRT2_INP_DIS
Address3__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
Address3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Address3__LCD_EN EQU CYREG_PRT2_LCD_EN
Address3__MASK EQU 0x04
Address3__PORT EQU 2
Address3__PRT EQU CYREG_PRT2_PRT
Address3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Address3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Address3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Address3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Address3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Address3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Address3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Address3__PS EQU CYREG_PRT2_PS
Address3__SHIFT EQU 2
Address3__SLW EQU CYREG_PRT2_SLW

/* Address4 */
Address4__0__INTTYPE EQU CYREG_PICU2_INTTYPE3
Address4__0__MASK EQU 0x08
Address4__0__PC EQU CYREG_PRT2_PC3
Address4__0__PORT EQU 2
Address4__0__SHIFT EQU 3
Address4__AG EQU CYREG_PRT2_AG
Address4__AMUX EQU CYREG_PRT2_AMUX
Address4__BIE EQU CYREG_PRT2_BIE
Address4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Address4__BYP EQU CYREG_PRT2_BYP
Address4__CTL EQU CYREG_PRT2_CTL
Address4__DM0 EQU CYREG_PRT2_DM0
Address4__DM1 EQU CYREG_PRT2_DM1
Address4__DM2 EQU CYREG_PRT2_DM2
Address4__DR EQU CYREG_PRT2_DR
Address4__INP_DIS EQU CYREG_PRT2_INP_DIS
Address4__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
Address4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Address4__LCD_EN EQU CYREG_PRT2_LCD_EN
Address4__MASK EQU 0x08
Address4__PORT EQU 2
Address4__PRT EQU CYREG_PRT2_PRT
Address4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Address4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Address4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Address4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Address4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Address4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Address4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Address4__PS EQU CYREG_PRT2_PS
Address4__SHIFT EQU 3
Address4__SLW EQU CYREG_PRT2_SLW

/* BoardTherm1 */
BoardTherm1__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
BoardTherm1__0__MASK EQU 0x40
BoardTherm1__0__PC EQU CYREG_PRT6_PC6
BoardTherm1__0__PORT EQU 6
BoardTherm1__0__SHIFT EQU 6
BoardTherm1__AG EQU CYREG_PRT6_AG
BoardTherm1__AMUX EQU CYREG_PRT6_AMUX
BoardTherm1__BIE EQU CYREG_PRT6_BIE
BoardTherm1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BoardTherm1__BYP EQU CYREG_PRT6_BYP
BoardTherm1__CTL EQU CYREG_PRT6_CTL
BoardTherm1__DM0 EQU CYREG_PRT6_DM0
BoardTherm1__DM1 EQU CYREG_PRT6_DM1
BoardTherm1__DM2 EQU CYREG_PRT6_DM2
BoardTherm1__DR EQU CYREG_PRT6_DR
BoardTherm1__INP_DIS EQU CYREG_PRT6_INP_DIS
BoardTherm1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BoardTherm1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BoardTherm1__LCD_EN EQU CYREG_PRT6_LCD_EN
BoardTherm1__MASK EQU 0x40
BoardTherm1__PORT EQU 6
BoardTherm1__PRT EQU CYREG_PRT6_PRT
BoardTherm1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BoardTherm1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BoardTherm1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BoardTherm1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BoardTherm1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BoardTherm1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BoardTherm1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BoardTherm1__PS EQU CYREG_PRT6_PS
BoardTherm1__SHIFT EQU 6
BoardTherm1__SLW EQU CYREG_PRT6_SLW

/* BoardTherm2 */
BoardTherm2__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
BoardTherm2__0__MASK EQU 0x80
BoardTherm2__0__PC EQU CYREG_PRT6_PC7
BoardTherm2__0__PORT EQU 6
BoardTherm2__0__SHIFT EQU 7
BoardTherm2__AG EQU CYREG_PRT6_AG
BoardTherm2__AMUX EQU CYREG_PRT6_AMUX
BoardTherm2__BIE EQU CYREG_PRT6_BIE
BoardTherm2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BoardTherm2__BYP EQU CYREG_PRT6_BYP
BoardTherm2__CTL EQU CYREG_PRT6_CTL
BoardTherm2__DM0 EQU CYREG_PRT6_DM0
BoardTherm2__DM1 EQU CYREG_PRT6_DM1
BoardTherm2__DM2 EQU CYREG_PRT6_DM2
BoardTherm2__DR EQU CYREG_PRT6_DR
BoardTherm2__INP_DIS EQU CYREG_PRT6_INP_DIS
BoardTherm2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BoardTherm2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BoardTherm2__LCD_EN EQU CYREG_PRT6_LCD_EN
BoardTherm2__MASK EQU 0x80
BoardTherm2__PORT EQU 6
BoardTherm2__PRT EQU CYREG_PRT6_PRT
BoardTherm2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BoardTherm2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BoardTherm2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BoardTherm2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BoardTherm2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BoardTherm2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BoardTherm2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BoardTherm2__PS EQU CYREG_PRT6_PS
BoardTherm2__SHIFT EQU 7
BoardTherm2__SLW EQU CYREG_PRT6_SLW

/* BoardTherm3 */
BoardTherm3__0__INTTYPE EQU CYREG_PICU5_INTTYPE0
BoardTherm3__0__MASK EQU 0x01
BoardTherm3__0__PC EQU CYREG_PRT5_PC0
BoardTherm3__0__PORT EQU 5
BoardTherm3__0__SHIFT EQU 0
BoardTherm3__AG EQU CYREG_PRT5_AG
BoardTherm3__AMUX EQU CYREG_PRT5_AMUX
BoardTherm3__BIE EQU CYREG_PRT5_BIE
BoardTherm3__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm3__BYP EQU CYREG_PRT5_BYP
BoardTherm3__CTL EQU CYREG_PRT5_CTL
BoardTherm3__DM0 EQU CYREG_PRT5_DM0
BoardTherm3__DM1 EQU CYREG_PRT5_DM1
BoardTherm3__DM2 EQU CYREG_PRT5_DM2
BoardTherm3__DR EQU CYREG_PRT5_DR
BoardTherm3__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm3__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm3__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm3__MASK EQU 0x01
BoardTherm3__PORT EQU 5
BoardTherm3__PRT EQU CYREG_PRT5_PRT
BoardTherm3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm3__PS EQU CYREG_PRT5_PS
BoardTherm3__SHIFT EQU 0
BoardTherm3__SLW EQU CYREG_PRT5_SLW

/* BoardTherm4 */
BoardTherm4__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
BoardTherm4__0__MASK EQU 0x02
BoardTherm4__0__PC EQU CYREG_PRT5_PC1
BoardTherm4__0__PORT EQU 5
BoardTherm4__0__SHIFT EQU 1
BoardTherm4__AG EQU CYREG_PRT5_AG
BoardTherm4__AMUX EQU CYREG_PRT5_AMUX
BoardTherm4__BIE EQU CYREG_PRT5_BIE
BoardTherm4__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm4__BYP EQU CYREG_PRT5_BYP
BoardTherm4__CTL EQU CYREG_PRT5_CTL
BoardTherm4__DM0 EQU CYREG_PRT5_DM0
BoardTherm4__DM1 EQU CYREG_PRT5_DM1
BoardTherm4__DM2 EQU CYREG_PRT5_DM2
BoardTherm4__DR EQU CYREG_PRT5_DR
BoardTherm4__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm4__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm4__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm4__MASK EQU 0x02
BoardTherm4__PORT EQU 5
BoardTherm4__PRT EQU CYREG_PRT5_PRT
BoardTherm4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm4__PS EQU CYREG_PRT5_PS
BoardTherm4__SHIFT EQU 1
BoardTherm4__SLW EQU CYREG_PRT5_SLW

/* BoardTherm5 */
BoardTherm5__0__INTTYPE EQU CYREG_PICU5_INTTYPE2
BoardTherm5__0__MASK EQU 0x04
BoardTherm5__0__PC EQU CYREG_PRT5_PC2
BoardTherm5__0__PORT EQU 5
BoardTherm5__0__SHIFT EQU 2
BoardTherm5__AG EQU CYREG_PRT5_AG
BoardTherm5__AMUX EQU CYREG_PRT5_AMUX
BoardTherm5__BIE EQU CYREG_PRT5_BIE
BoardTherm5__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm5__BYP EQU CYREG_PRT5_BYP
BoardTherm5__CTL EQU CYREG_PRT5_CTL
BoardTherm5__DM0 EQU CYREG_PRT5_DM0
BoardTherm5__DM1 EQU CYREG_PRT5_DM1
BoardTherm5__DM2 EQU CYREG_PRT5_DM2
BoardTherm5__DR EQU CYREG_PRT5_DR
BoardTherm5__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm5__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm5__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm5__MASK EQU 0x04
BoardTherm5__PORT EQU 5
BoardTherm5__PRT EQU CYREG_PRT5_PRT
BoardTherm5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm5__PS EQU CYREG_PRT5_PS
BoardTherm5__SHIFT EQU 2
BoardTherm5__SLW EQU CYREG_PRT5_SLW

/* BoardTherm6 */
BoardTherm6__0__INTTYPE EQU CYREG_PICU5_INTTYPE3
BoardTherm6__0__MASK EQU 0x08
BoardTherm6__0__PC EQU CYREG_PRT5_PC3
BoardTherm6__0__PORT EQU 5
BoardTherm6__0__SHIFT EQU 3
BoardTherm6__AG EQU CYREG_PRT5_AG
BoardTherm6__AMUX EQU CYREG_PRT5_AMUX
BoardTherm6__BIE EQU CYREG_PRT5_BIE
BoardTherm6__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm6__BYP EQU CYREG_PRT5_BYP
BoardTherm6__CTL EQU CYREG_PRT5_CTL
BoardTherm6__DM0 EQU CYREG_PRT5_DM0
BoardTherm6__DM1 EQU CYREG_PRT5_DM1
BoardTherm6__DM2 EQU CYREG_PRT5_DM2
BoardTherm6__DR EQU CYREG_PRT5_DR
BoardTherm6__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm6__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm6__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm6__MASK EQU 0x08
BoardTherm6__PORT EQU 5
BoardTherm6__PRT EQU CYREG_PRT5_PRT
BoardTherm6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm6__PS EQU CYREG_PRT5_PS
BoardTherm6__SHIFT EQU 3
BoardTherm6__SLW EQU CYREG_PRT5_SLW

/* BoardTherm7 */
BoardTherm7__0__INTTYPE EQU CYREG_PICU5_INTTYPE4
BoardTherm7__0__MASK EQU 0x10
BoardTherm7__0__PC EQU CYREG_PRT5_PC4
BoardTherm7__0__PORT EQU 5
BoardTherm7__0__SHIFT EQU 4
BoardTherm7__AG EQU CYREG_PRT5_AG
BoardTherm7__AMUX EQU CYREG_PRT5_AMUX
BoardTherm7__BIE EQU CYREG_PRT5_BIE
BoardTherm7__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm7__BYP EQU CYREG_PRT5_BYP
BoardTherm7__CTL EQU CYREG_PRT5_CTL
BoardTherm7__DM0 EQU CYREG_PRT5_DM0
BoardTherm7__DM1 EQU CYREG_PRT5_DM1
BoardTherm7__DM2 EQU CYREG_PRT5_DM2
BoardTherm7__DR EQU CYREG_PRT5_DR
BoardTherm7__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm7__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm7__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm7__MASK EQU 0x10
BoardTherm7__PORT EQU 5
BoardTherm7__PRT EQU CYREG_PRT5_PRT
BoardTherm7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm7__PS EQU CYREG_PRT5_PS
BoardTherm7__SHIFT EQU 4
BoardTherm7__SLW EQU CYREG_PRT5_SLW

/* BoardTherm8 */
BoardTherm8__0__INTTYPE EQU CYREG_PICU5_INTTYPE5
BoardTherm8__0__MASK EQU 0x20
BoardTherm8__0__PC EQU CYREG_PRT5_PC5
BoardTherm8__0__PORT EQU 5
BoardTherm8__0__SHIFT EQU 5
BoardTherm8__AG EQU CYREG_PRT5_AG
BoardTherm8__AMUX EQU CYREG_PRT5_AMUX
BoardTherm8__BIE EQU CYREG_PRT5_BIE
BoardTherm8__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm8__BYP EQU CYREG_PRT5_BYP
BoardTherm8__CTL EQU CYREG_PRT5_CTL
BoardTherm8__DM0 EQU CYREG_PRT5_DM0
BoardTherm8__DM1 EQU CYREG_PRT5_DM1
BoardTherm8__DM2 EQU CYREG_PRT5_DM2
BoardTherm8__DR EQU CYREG_PRT5_DR
BoardTherm8__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm8__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm8__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm8__MASK EQU 0x20
BoardTherm8__PORT EQU 5
BoardTherm8__PRT EQU CYREG_PRT5_PRT
BoardTherm8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm8__PS EQU CYREG_PRT5_PS
BoardTherm8__SHIFT EQU 5
BoardTherm8__SLW EQU CYREG_PRT5_SLW

/* BoardTherm9 */
BoardTherm9__0__INTTYPE EQU CYREG_PICU5_INTTYPE6
BoardTherm9__0__MASK EQU 0x40
BoardTherm9__0__PC EQU CYREG_PRT5_PC6
BoardTherm9__0__PORT EQU 5
BoardTherm9__0__SHIFT EQU 6
BoardTherm9__AG EQU CYREG_PRT5_AG
BoardTherm9__AMUX EQU CYREG_PRT5_AMUX
BoardTherm9__BIE EQU CYREG_PRT5_BIE
BoardTherm9__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BoardTherm9__BYP EQU CYREG_PRT5_BYP
BoardTherm9__CTL EQU CYREG_PRT5_CTL
BoardTherm9__DM0 EQU CYREG_PRT5_DM0
BoardTherm9__DM1 EQU CYREG_PRT5_DM1
BoardTherm9__DM2 EQU CYREG_PRT5_DM2
BoardTherm9__DR EQU CYREG_PRT5_DR
BoardTherm9__INP_DIS EQU CYREG_PRT5_INP_DIS
BoardTherm9__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BoardTherm9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BoardTherm9__LCD_EN EQU CYREG_PRT5_LCD_EN
BoardTherm9__MASK EQU 0x40
BoardTherm9__PORT EQU 5
BoardTherm9__PRT EQU CYREG_PRT5_PRT
BoardTherm9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BoardTherm9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BoardTherm9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BoardTherm9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BoardTherm9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BoardTherm9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BoardTherm9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BoardTherm9__PS EQU CYREG_PRT5_PS
BoardTherm9__SHIFT EQU 6
BoardTherm9__SLW EQU CYREG_PRT5_SLW

/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 18
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E16C069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 18
CYDEV_CHIP_MEMBER_4D EQU 13
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 19
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 17
CYDEV_CHIP_MEMBER_4I EQU 23
CYDEV_CHIP_MEMBER_4J EQU 14
CYDEV_CHIP_MEMBER_4K EQU 15
CYDEV_CHIP_MEMBER_4L EQU 22
CYDEV_CHIP_MEMBER_4M EQU 21
CYDEV_CHIP_MEMBER_4N EQU 10
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 20
CYDEV_CHIP_MEMBER_4Q EQU 12
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 11
CYDEV_CHIP_MEMBER_4T EQU 9
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_4V EQU 16
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 24
CYDEV_CHIP_MEMBER_FM3 EQU 28
CYDEV_CHIP_MEMBER_FM4 EQU 29
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_ES EQU 17
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000007
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 5000
CYIPBLOCK_ARM_CM3_VERSION EQU 0
CYIPBLOCK_P3_ANAIF_VERSION EQU 0
CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
CYIPBLOCK_P3_COMP_VERSION EQU 0
CYIPBLOCK_P3_DMA_VERSION EQU 0
CYIPBLOCK_P3_DRQ_VERSION EQU 0
CYIPBLOCK_P3_EMIF_VERSION EQU 0
CYIPBLOCK_P3_I2C_VERSION EQU 0
CYIPBLOCK_P3_LCD_VERSION EQU 0
CYIPBLOCK_P3_LPF_VERSION EQU 0
CYIPBLOCK_P3_OPAMP_VERSION EQU 0
CYIPBLOCK_P3_PM_VERSION EQU 0
CYIPBLOCK_P3_SCCT_VERSION EQU 0
CYIPBLOCK_P3_TIMER_VERSION EQU 0
CYIPBLOCK_P3_USB_VERSION EQU 0
CYIPBLOCK_P3_VIDAC_VERSION EQU 0
CYIPBLOCK_P3_VREF_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 0
CYIPBLOCK_S8_IRQ_VERSION EQU 0
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x00000003
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
